EPICURE: A partitioning and co-design framework for reconfigurable computing

This paper presents a new design methodology able to bridge the gap between an abstract specification and a heterogeneous reconfigurable architecture. The EPICURE contribution is the result of a joint study on abstraction/refinement methods and a smart reconfigurable architecture within the formal Esterel design tools suite. The original points of this work are: (i) a generic HW/SW interface model, (ii) a specification methodology that handles the control, and includes efficient verification and HW/SW synthesis capabilities, (iii) a method for parallelism exploration based on abstract resources/performance estimation expressed in terms of area/delay tradeoffs, (iv) a HW/SW partitioning approach that refines the specification into explicit HW configurations and the associated SW control. The EPICURE framework shows how a cooperation of complementary methodologies and CAD tools associated with a relevant architecture can signficantly improve the designer productivity, especially in the context of reconfigurable architectures

Exploration Architecturale au Niveau Comportemental - Application aux FPGAs

A significant factor in the evolution of modern electronic systems is the appearance of new architectures based on the programming of hardware components such as Field programmable Gate Arrays (FPGAs). The introduction of those components as an alternative computation unit and the flexibility they offer increase the interest of suche an integration solution. Moreover, the recent evolutions of the different families allow today the implementation of complex systems with higher constraints on performances. Few works focus on the estimation of an application on a technology of this type. Until now, researchers mainly carried their efforts on the imrpovement of reconfigurable architectures in order to make them powerful and thus to constitute an alternative to ASICs (Application Specific Integrated Circuits). The objective of the work presented in this thesis is to propose techniques and tools associated on programmable architectures. The developed method is generic (it can be applied to several FPGA families) and is located at the behavioral level. It allows the browsing of several architectural solutions and is integrated in a hardware : software codesign methodology.Un facteur important dans l'évolution des systèmes électroniques modernes est l'apparition de nouvelles architectures basées sur la programmation de circuits matériels tels que les composants programmables. Les récentes évolutions des différentes familles autorisent aujourd'hui l'intégration de systèmes de plus en plus complexes avec des contraintes de performances de plus en plus fortes. D'autre part, la flexibilité offerte par ce type de technologie fait des FPGAs (Field programmable gate arrays) une cible architecturale promise à un bel avenir. L'évaluation des performances d'une application sur une technologie reconfigurable est un problème peu étudié à ce jour. Jusqu'à présent, les chercheurs ont principalement porté leurs efforts sur l'amélioration des architectures afin de les rendre plus performantes et ainsi constituer une réelle alternative aux ASICs (Application specific integrated circuits). L'objectif du travail présenté dans ce mémoire consiste à proposer des techniques et les outils associés permettant l'évaluation rapide des performances (temps, surface) d'applications sur des architectures programmables. La méthode développée est générique (elle s'applique à plusieurs familles de FPGAs) et se situe au niveau comportemental. Elle permet l'exploration de plusieurs solutions architecturales et s'intègre dans un flot de conception conjointe logiciel / matériel

Modélisation, Conception Système d'Architectures Hétérogènes pour les Applications Embarquées: Eléments d'amélioration de l'efficacité énergétique des systèmes sur puce de silicium

Next level of energy efficiency is an essential concern in the evolution of semiconductor technologies sincethe widespread development of distributed, nomad and embedded systems. The best example is that ofmobile phones the last twenty years but consumer electronics perspectives (IoT, 5G, HPC, ArtificialIntelligence, Robotics, automotive engineering) reinforce the need for further power consumption control.The research carried out for this habilitation defense addresses this question by investigating tools andmethodologies for digital system design focusing on energy constraints and embedded technologies. Inparticular, all the investigations developed over the last fifteen years are part of ambitious collaborativeprojects with representative industrial partners (Intel, Thales, STMicroelectronics, etc.) on different aspectsof energy concerns. Despite the difficulty faced today to proceed with a fundamental study on the long runin a global context of applied research (collaborative projects funded for 3 or 4 years with objectives highlydriven by industrial R&D), it is a deliberate approach aimed at setting the short-term views of projectproposals in a broader scientific horizon which has made it possible to identify and develop original ideason more fundamental questions. These elements of improvement have led to propose a methodologycentered on energy efficiency reflecting a concept of integrated design methodology with case studiesreporting significant improvements on concrete demonstrators.Les enjeux d’une meilleure efficacité énergétique sont un moteur essentiel de l’évolution des technologiessemi-conducteur depuis la popularisation des systèmes répartis, nomades et embarqués. L’exemple le plusparlant est celui des téléphones portables ces vingt dernières années et les perspectives technologiques(IoT, 5G, HPC, intelligence artificielle, Robotique, ingénierie automobile) renforcent encore plus la nécessitéde la maîtrise de la consommation d’énergie. Les travaux de recherche qui ont conduit à cette HDRabordent cette question par l’étude d’outils et de méthodes de conception des systèmes numériques en sefocalisant sur les contraintes énergétiques et les technologies embarquées. En particulier, les rechercheseffectuées ces quinze dernières années interviennent toutes au sein de projets collaboratifs ambitieux avecdes industriels représentatifs du domaine (Intel, Thales, STMicroelectronics, etc.) sur les aspectsénergétiques. Malgré les difficultés à poursuivre aujourd’hui une étude fondamentale sur la durée dans uncontexte global de recherche appliquée (projets collaboratifs financés à trois ou quatre ans sur des enjeuxfortement influencés par la R&D industrielle), c’est une démarche délibérée visant à intégrer lesperspectives à court terme des appels d’offre dans un horizon scientifique plus large qui a permisd’identifier et d’approfondir des idées originales sur des aspects plus fondamentaux. Ces élémentsd’amélioration ont conduit à envisager une méthodologie centrée sur l’efficacité énergétique qui reflète unconcept de conception intégrée avec des études de cas montrant des améliorations significatives sur desdémonstrateurs concrets

Hardware Acceleration of Real-Life Applications: from Theory to Implementation

There has been a lot of research to support the benefits of reconfigurable hardware acceleration in high performance low power System-on-Chips. Despite numerous advances made over the last two decades, especially in code generation support, reconfigurable system-on-chips still face application programming challenges. As the full automated synthesis of real-world applications such as digital video coding is still not supported for complexity reasons, acceleration is likely to occur as an execution of software code and dedicated hardware involving large amounts of data communication. These overheads alter significantly the benefits of hardware acceleration and usually requires important hardware expertise. In these conditions, a bottleneck lies in the fast implementation of optimised on-chip bus interfaces, indeed this time consuming hardware (and software) development process reflects critically on performance, but also on development and debug efforts. This paper proposes a design flow for reconfigurable hardware acceleration in which a specific topology for C/C++ function arguments is set to help the generation of on-chip bus compliant interface, on top of High Level Synthesis (HLS). We show how struc-turing data arguments allows the definition of a generic bus wrapper interface for accelerators produced by HLS. We additionally illustrate the effectiveness of this approach on the practical implementation example of a full H264/AVC profile video decoder in recent FPGA-embedded systems considering PLB and AXI bus protocols

Exploration architecturale au niveau comportemental (application aux FPGAs)

A significant factor in the evolution of modern electronic systems is the appearance of new architectures based on the programming of hardware components such as Field programmable Gate Arrays (FPGAs). The introduction of those components as an alternative computation unit and the flexibility they offer increase the interest of suche an integration solution. Moreover, the recent evolutions of the different families allow today the implementation of complex systems with higher constraints on performances. Few works focus on the estimation of an application on a technology of this type. until now, researchers mainly carried their efforts on the imrpovement of reconfigurable architectures in order to make them powerful and thus to constitute an alternative to ASICs (Application Specific Integrated Circuits). the objective of the work presented in this thesis is to propose techniques and tools associated on programmable architectures. the developed method is generic (it can be applied to several FPGA families) and is located at the behavioral level. it allows the browsing of several architectural solutions and is integrated in a hardware : software codesign methodology.Un facteur important dans l'évolution des systèmes électroniques modernes est l'apparition de nouvelles architectures basées sur la programmation de circuits matériels tels que les composants programmables. Les récentes évolutions des différentes familles autorisent aujourd'hui l'intégration de systèmes de plus en plus complexes avec des contraintes de performances de plus en plus fortes. D'autre part, la flexibilité offerte par ce type de technologie fait des FPGAs (Field programmable gate arrays) une cible architecturale promise à un bel avenir. L'évaluation des performances d'une application sur une technologie reconfigurable est un problème peu étudié à ce jour. Jusqu'à présent, les chercheurs ont principalement porté leurs efforts sur l'amélioration des architectures afin de les rendre plus performantes et ainsi constituer une réelle alternative aux ASICs (Application specific integrated circuits). L'objectif du travail présenté dans ce mémoire consiste à proposer des techniques et les outils associés permettant l'évaluation rapide des performances (temps, surface) d'applications sur des architectures programmables. La méthode développée est générique (elle s'applique à plusieurs familles de FPGAs) et se situe au niveau comportemental. Elle permet l'exploration de plusieurs solutions architecturales et s'intègre dans un flot de conception conjointe logiciel / matériel.LORIENT-BU (561212106) / SudocSudocFranceF

A hardware software co design methodology for heterogeneous architecture estimation

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An Energy-Aware Scheduler for Dynamically Reconfigurable Multi-Core Systems

International audienceThis paper describes an energy-aware scheduling approach intended for use in heterogeneous multiprocessors supporting hardware acceleration with Dynamic and Partial Re-configuration. Scheduler decisions rely on pragmatic power and energy models to map the load across cores and reconfigurable regions with regards to the actual power costs. Results on a multithreaded H.264/AVC profile decoder with three possible hardware functions on a Xilinx Zynq based platform report energy gains up to 44.1% over full software execution and 49.6% over static hardware / software execution, while ensuring real-time decoding requirement

Area Time Power Estimation for FPGA Based Designs at a Behavioral Level

A new performance estimation technique for FPGA implementation based designs is presented. The interest and originality of the method is to rapidly test a great number of implementation solutions while staying independent as far as possible of the technology used, and to include power consumption estimation. Thanks to this method, the designer can quickly have realistic information about the performances of a design, starting from a behavioral specification. 1

Method for scheduling with deadline constraints, in particular in linux, carried out in user space

A method for scheduling tasks with deadline constraints, based on a model of independent periodic tasks and carried out in the user space by means of API POSIX. http://patentscope.wipo.int/search/en/WO201407290

FPGA area time power estimation for DSP applications

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